library ieee;
use ieee.std_logic_1164.all;

package ALU_components_pack is

      
      
        
   -- Button debouncing 
-------------------------------------------------------------------------------
-- debouncer component: There is no need to use this component, though if you get 
--                      unwanted moving between states of the FSM because of pressing
--                      push-button this component might be useful.
-------------------------------------------------------------------------------


   component debouncer   
       port(
           rst, clk: in std_logic;
           button_in: in std_logic;
           button_out: out std_logic
           );
   end component;        
           
   
   
      
      
		  -- General D-flipflop
    component dff
      generic (
        w : integer);
      port (
        clk, rst : in  std_logic;
        d        : in  std_logic_vector(w-1 downto 0);
        q        : out std_logic_vector(w-1 downto 0));
    end component;







      -- Add more components here. These can be small components you may need to complete the other codes.
      -- For example simple adder, subtractor, comparator, 2-to-1 multiplexer as well as ADD3 needed in Binary-to-BCD converter
      -- can be included in this file. 
      
      
      
      

end ALU_components_pack;



-------------------------------------------------------------------------------
-- ALU component pack body
-------------------------------------------------------------------------------





-------------------------------------------------------------------------------
-- debouncer component
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity debouncer is
   port (
          rst, clk: in std_logic;
           button_in: in std_logic;
           button_out: out std_logic
         );
end debouncer;




architecture behavioral of debouncer is
    
    signal count : unsigned(19 downto 0); -- range to count 20ms with 50 MHz clock
    signal button_tmp : std_logic;
begin

process(rst, clk)
begin
  if rst = '1' then
         count <= (others => '0');
  elsif rising_edge(clk) then
         count <=  count + 1;
         button_tmp <= button_in;
      if (count = 0) then
         button_out <= button_tmp;
      end if;
  end if;
  
end process;

end behavioral;



------------------------------------------------------------------------------
-- component dff
-------------------------------------------------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;

    entity dff is
      
      generic (
        w : integer);

      port (
        clk, rst : in  std_logic;
        d        : in  std_logic_vector(w-1 downto 0);
        q        : out std_logic_vector(w-1 downto 0));

    end dff;

    architecture behavioral of dff is

    begin  -- behavioral
        

        process(clk)
           begin
              if(clk'event and clk='1') then 
                if(rst='1') then
                   q <= (others => '0');
                else
                   q <= d;
               end if;
              end if;
         end process;              

    end behavioral;

-------------------------------------------------------------------------------
-- Include the body code for the rest of small components here
-------------------------------------------------------------------------------

